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Senior Staff Digital Design Engineer
About Marvell Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. Your Team, Your Impact As a Digital IC Design Senior Staff Engineer with Marvell, you’ll be a member of the Connectivity business group. Pushing the limits in communication with focus on data center and enabling AI infrastructure. This team hires some of the biggest problem solvers in Silicon and has a huge impact on the work done at Marvell. The customers served by this team are often other chip companies and big tech companies, familiar names to all candidates. What You Can Expect -Develop RTL designs using Verilog/SystemVerilog for digital IP blocks and subsystems. -Translate architectural specifications into clean, synthesizable RTL -Perform linting, CDC and low-power design checks -Analyze timing, area, and power tradeoffs during design implementation -Support synthesis and work with physical design teams on timing closure issues. -Debug functional issues discovered during simulation, emulation, FPGA prototyping or silicon bring-up What We're Looking For To be successful in this role, you must: - Have a Bachelor’s or Master’s in Electrical Engineering, Computer Engineering, Computer Science, or similar field. Degrees in mathematics, physics or other sciences may be considered provided adequate coursework in electronics was taken also or work experience has provided relevant knowledge since graduation. - Independently analyzes and optimizes small sub-circuit blocks within our overall design across Process, Voltage, Temperature • Responsible engineer for at least one major sub-circuit block from architecture definition to fine tuning. • Identifies and proposes innovative solutions to enhance the design of at least one major sub-circuit block. • Participates in root cause investigation and silicon validation of model to hardware correlation issues. • Mentors and coaches new and/or less experienced team members. -Knowledge of communication and DSP algorithms preferred -Verification experience with preference in UVM is a big plus. Expected Base Pay Range (USD) 135,900 - 201,130, $ per annum The successful candidate’s starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions. The expected base pay range for this role may be modified based on market conditions. Additional Compensation and Benefit Elements Marvell is committed to providing exceptional, comprehensive benefits that support our employees at every stage - from internship to retirement and through life’s most important moments. Our offerings are built around four key pillars: financial well-being, family support, mental and physical health, and recognition. Highlights include an employee stock purchase plan with a 2-year look back, family support programs to help balance work and home life, robust mental health resources to prioritize emotional well-being, and a recognition and service awards to celebrate contributions and milestones. We look forward to sharing more with you during the interview process. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status. Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at TAOps@marvell.com. Interview Integrity To support fair and authentic hiring practices, candidates are not permitted to use AI tools (such as transcription apps, real-time answer generators like ChatGPT or Copilot, or automated note-taking bots) during interviews. These tools must not be used to record, assist with, or enhance responses in any way. Our interviews are designed to evaluate your individual experience, thought process, and communication skills in real time. Use of AI tools without prior instruction from the interviewer will result in disqualification from the hiring process. This position may require access to technology and/or software subject to U.S. export control laws and regulations, including the Export Administration Regulations (EAR). As such, applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens, lawful permanent residents, or protected individuals as defined by 8 U.S.C. 1324b(a)(3), all applicants may be subject to an export license review process prior to employment. #LI-JT2
